基于FPGA的1553B总线编解码模块的设计与改进

Design and Improvement of Coding and Decoding Moduleof 1553B Bus Based on FPGA

摘要:

针对现有 1553B总线编解码器结构设计复杂、编解码实时性较差的问题,提出了一种改进的编解码方法。利用寄存器按位进行曼彻斯特编码,提高了整体的编码效率。利用移位寄存器对同步头进行匹配,实现了快速解码。仿真结果表明:该设计简化了编解码逻辑,完整实现了1553B总线的编解码功能。

Abstract:

To solve the problems of complex design and poor real-time performance oicoding and decoding for 1553B bus, an improved method of coding and decoding is proposedRegisters are used for Manchester coding by bits, which improves the overall codingefficiency. Shift registers are used to match synchronization word for fast decoding. Thesimulation results show that the method simplifies the coding logic and decoding logic. Thefunction of coding and decoding is realized for 1553B bus.