面向舰船检测的神经网络加速器设计

Design of Neural Network Accelerator for Ship Recognition

摘要:

针对卫星遥感图像的舰船目标检测需求,设计了基于现场可编程门阵列(Field Programmable GateArray,FPGA)的卷积神经网络(Convolution Neural Network,CNN)加速器。运算单元采用多层次并行化结构,底层采用乘法器级并行结构,使用行缓存单元优化数据流;顶层采用模块级并行结构,可灵活调整输出通道的并行度。针对片外数据访问延时高的问题,提出了基于FPGA 块随机存储器(Block Random Access Memory,BRAM)的阵列式片上数据缓存单元,保证数据的实时读取和数据流的灵活分配。实验结果表明:加速器移植到XilinxKC705 开发平台,工作频率达100 MHz,平均吞吐率为217 GOPS,能效比为86.8GOPS/W,对连续遥感舰船图像的检测速率可达105帧/秒。

Abstract:

In response to the requirements of ship target detection in satellite remotesensing images, a convolution neural network ( CNN) accelerator based on fieldprogrammable gate array (FPGA) is designed, The computing unit adopts a multi-levelparallel design, The bottom layer adopts multiplier-level parallelism, and the line buffer unitis used to optimize data flow. The top layer adopts module-level parallelism, which canflexibly adjust the parallelism of the output channels. Aiming at the problem of high latencyof off-chip data access, an array-type on-chip data cache unit based on FPGA block randomaccess memory ( BRAM) is proposed to ensure real-time data reading and flexibldistribution of data streams. Experimental results show that the accelerator is deploved onthe Xilinx KC705 development platform, with working frequency of 100 MHz, average throughput rate of 217 GOPS, energy efficiency ratio of 86. 8 GOPs/W, and detection rate ofup to 105 frames per second for continuous remote sensing ship images.